The present invention relates to a semiconductor integrated circuit device having its layout designed by a cell base system, that is, by a system that lays out a logic circuit for each standard cell.
FIG. 1 is a layout sketch depicting a semiconductor integrated circuit device that utilizes the cell base system for its layout design. In FIG. 1, reference numeral 1 denotes the semiconductor integrated circuit device, 2 standard cells (hereinafter referred to also simply as cells) forming the semiconductor integrated circuit device 1, 3a to 3g cell arrays each consisting of a predetermined number of standard cells 2 arranged side by side, 4 intercell conductors between the cells 2 and 2, 5 I/O pads for signal input/output therethrough, 5a I/O conductors between the I/O pads 5 and the cells 2, 6 power supply pads, 7 grounding pads, 8 power supply conductors, and 9 grounding conductors.
The standard cells 2, which constitute the cell arrays 3a to 3g, include various logic circuits such as inverters, AND, OR, NAND and NOR gates and flip-flops. In FIG. 3 there is shown an example that an inverter depicted in FIG. 2 is the standard cell of a CMOS configuration. In FIG. 3, reference numeral 10 denotes a P-channel MOS transistor (hereinafter referred to as a PMOS), 11 an N-channel MOS transistor (hereinafter referred to as an NMOS), 12 a PMOS source conductor, 13a a PMOS gate conductor, 13b an NMOS-side gate conductor, 14 a common drain conductor, 15 an NMOS source conductor, 16 a cell power supply conductor, 17 a cell grounding conductor, 18 an input pin of the inverter, 19 an output pin of the inverter, 20a a through hole for interconnecting the input pin 18 and an Al conductor, 20b a through hole interconnecting the output pin 19 and the common drain conductor 14, and 21 a through hole interconnecting the Al conductor and the gate conductors 13a and 13b. 
In the inverter cell depicted in FIG. 3, the cell power supply conductor 16, the cell grounding conductor 17, the PMOS source conductor 12, the common drain conductor 14 and the NMOS source conductor 15 are a first Al wiring layer. The standard cells of NAND gates, flip-flops and so on, as well as the inverters, have their cell power supply conductors 16 and their cell grounding conductors 17 formed from the first Al wiring layer. Accordingly, adjacent cells 2 of the respective cell arrays 3a to 3g have their cell power supply conductors 16 and their cell grounding conductors 17 interconnected via the first Al wiring layer. The signal transmission between the standard cells is made via a second Al wiring layer.
In the semiconductor integrated circuit device whose layout is designed using the cell base system, the standard cell width needs to be defined since the cell arrays 3a to 3g are a side-by-side arrangement of plural standard cells 2. It is customary in the art to set, as one basic cell width (1 BC), a width 24 which is half that 22 of the inverter cell depicted in FIG. 3. With such a basic cell (BC), the width 22 of the inverter cell shown in FIG. 3 is 2 BC.
On the other hand, the height 23 of the inverter cell depicted in FIG. 3 is called the cell height, and in the cell bases system, to keep the cell arrays 3a to 3g at a fixed height is most important for continuously connecting the cell power supply conductor 16 and the cell grounding conductor 17 without a break; hence, the cell height is set at a fixed value irrespective of the kinds of standard cells used.
Next, the operation of the prior art example will be described.
A description will be given first of a method of layout design by the cell base system.
FIG. 4 is a diagram of an example in which three cell arrays 3a, 3b and 3c are formed by arranging side by side such standard cells as inverters, NAND gates and flip-flops. Since the cell widths of the individual standard cells are integral multiples of the basic cell width (1 BC), the widths of the cell arrays are integral multiples of 1 BC. However, the standard cells each have a different width; for example, the inverter cell width is 2 BC, the NAND cell width 3 BC and the flip-flop cell 15 BC. Therefore, the widths 26a, 26b and 26c of the three cell arrays 3a, 3b and 3c depicted in FIG. 4 differ from one another. In the FIG. 4 example, the width 26b of the cell array 3b and the width 26c of the cell array 3c are smaller than the longest cell array 3a by 4 BC and 2 BC, respectively.
To make the widths of the three cell arrays 3a, 3b and 3c equal, a feedthrough cell 28 shown in FIG. 5 is used. The width 27 of the feedthrough cell 28 is 1 BC and its cell height 23 is the same as those of the other standard cells. And this cell is made up only of a power supply conductor 16 and a cell grounding conductor 17 which are formed from the first Al wiring layer.
FIG. 6 shows an example in which such feedthrough cells 28 as depicted in FIG. 5 are inserted in the cell arrays 3b and 3c to make the widths of the three cell arrays 3a, 3b and 3c equal to one another. That is, four feedthrough cells 28a to 28d are additionally arranged in the cell array 3b and two feedthrough cells 28e and 28f are additionally arranged in the cell array 3c to make their array widths equal to that of the widest cell array 3a. 
The feedthrough cell 28 has a function of securing a wiring region as well as the function of providing the uniform cell array width as referred to above. This wiring region securing function will be described below. Now, consider the case where three cell arrays 3a, 3b and 3c of the same array width are completed by inserting appropriate numbers of feedthrough cells 28 as depicted in FIG. 6 and then a NAND cell in the cell array 3c and an inverter 32 in the cell array 3a are interconnected by a conductor 30 as depicted in FIG. 7. In this instance, as depicted in FIG. 8, the conductor 30 for connecting the NAND cell 31 of the cell array 3c and the inverter 32 of the cell array 3a crosses one of four feedthrough cells 28a to 28d of the cell array 3a, for example, the feedthrough cell 28b. Since the conductor 30 is formed from a second Al wiring layer, it does not contact the cell power supply conductor and grounding conductor of the feedthrough cell 28b formed from the first Al wiring layer.
Next, a description will be given of a method for supplying power to and grounding each cell array. As shown in FIG. 9, there are placed power supply/grounding cap cells 35 at opposite ends of the cell arrays 3a and 3b. Extending across the cap cells 35 are power supply conductors 33 and grounding conductors 34 formed from the second Al wiring layer. The power supply conductors 33 and the grounding conductors 34 are connected to the power supply pads 6 and the grounding pads 7, respectively, located on the marginal portions of the semiconductor integrated circuit device 1.
As depicted in FIG. 10, a power supply conductor 33a formed from the second Al wiring layer on each cap cell 35 is connected via a through hole 16a to a cell power supply conductor 16b formed from the first Al wiring layer, and similarly, a grounding conductor 34a formed from the second Al wiring layer is connected via a through hole 17a to a cell grounding conductor 17b formed from the first Al wiring layer. Since each cap cell 35 has the construction mentioned above, power is supplied to each cell via a route [power supply conductor 33a-through hole 16a-cell power supply conductor 16b] and each cell is grounded via a route [grounding conductor 34a-through hole 17a-cell grounding conductor 17b]. 
Since the semiconductor integrated circuit device having its layout designed by the conventional cell base system has the configuration described above, a design change after the completion of a layout plan with cell arrays of a uniform width would necessitate newly adding standard cells including inverters, AND, NAND, NOR and similar logic circuits; if the design change is made after the fabrication of exposure masks, it is necessary to produce again almost all of the expensive masks. This is time- and labor-consuming and inevitably raises manufacturing costs of the semiconductor integrated circuit device.
Incidentally, similar literature on the prior art is Japanese Pat. Laid-Open Gazette No. Hei 3-259549.
The present invention is intended to solve such problems as mentioned above, and has for its object to provide a semiconductor integrated circuit device whose layout is designed by the cell base system with which it is possible to flexibly deal with design changes.
A semiconductor integrated circuit device having its layout designed by the cell base system according to the invention claimed in claim 1 is provided with feedthrough cells each having a first basic pair made up of first and second gate electrodes for forming P- and N-channel MOS transistors, and first P-type and second N-type diffused layers formed at both sides of these first and second gate electrodes.
With such a configuration, even if a circuit modification involving newly adding an inverter, AND, NAND, NOR, or similar standard cell is required after the creation of a layout plan, a standard cell having such a logic circuit can be formed only by wiring the first basic pair; hence, it is possible to reduce the cost and time for the fabrication of exposure masks.
A semiconductor integrated circuit device having its layout designed by the cell base system according to the invention claimed in claim 2 is provided with cap cells each having a second basic pair made up of third and fourth gate electrodes for forming P- and N-channel MOS transistors, and third P-type and fourth N-type diffused layers formed at both sides of these first and second gate electrodes.
With such a configuration, even if a circuit modification involving newly adding an inverter, AND, NAND, NOR, or similar standard cell is required after the creation of a layout plan, a standard cell having such a logic circuit can be formed only by wiring the second basic pair; hence, it is possible to reduce the cost and time for the fabrication of exposure masks.
In a semiconductor integrated circuit device having its layout designed by the cell base system according to the invention claimed in claim 3, the second basic pair of the cap cell is prewired as predetermined to form a quasi-logic circuit which will ultimately form a desired logic circuit.
With such a configuration, even if a circuit modification involving newly adding an inverter, AND, NAND, NOR, or similar standard cell is required after the creation of a layout plan, a standard cell having such a logic circuit can be formed only by changing the wiring of the quasi-logic circuit; hence, it is possible to reduce the cost and time for the fabrication of exposure masks.
A semiconductor integrated circuit device having its layout designed by the cell base system according to the invention claimed in claim 4 is provided with: feedthrough cells each having a first basic pair made up of first and second gate electrodes for forming P- and N-channel MOS transistors, and first P-type and second N-type diffused layers formed at both sides of these first and second gate electrodes; and cap cells each having a second basic pair made up of third and fourth gate electrodes for forming P- and N-channel MOS transistors, and third P-type and fourth N-type diffused layers formed at both sides of these first and second gate electrodes.
With such a configuration, even if a circuit modification involving newly adding a flip-flop or similar large-scale standard cell as well as an inverter, AND, NAND, NOR, or similar small-scale standard cell is required after the creation of a layout plan, a standard cell having such a logic circuit can be formed only by wiring the first or second basic pair; hence, it is possible to reduce the cost and time for the fabrication of exposure masks.
In a semiconductor integrated circuit device having its layout designed by the cell base system according to the invention claimed in claim 5, the first and second basic pairs of the feedthrough cell and the cap cell are prewired as predetermined to form quasi-logic circuits which will ultimately form desired logic circuits.
With such a configuration, even if a circuit modification involving newly adding an inverter, AND, NAND, NOR, or similar standard cell is required after the creation of a layout plan, a standard cell having such a logic circuit can be formed only by changing the wiring each quasi-logic circuit; hence, it is possible to reduce the cost and time for the fabrication of exposure masks.
In a semiconductor integrated circuit device having its layout designed by the cell base system according to the invention claimed in claim 6, at least one part of the first and second basic pairs of the feedthrough cells and the cap cell are wired as predetermined to form desired logic circuits.
With such a configuration, even if a circuit modification involving newly adding a flip-flop or similar large-scale standard cell as well as an inverter, AND, NAND, NOR, or similar small-scale standard cell is required after the creation of a layout plan, a standard cell having such a logic circuit can be formed only by wiring the first or second basic pair; hence, it is possible to reduce the cost and time for the fabrication of exposure masks.
In the semiconductor integrated circuit device having its layout designed by a cell base system according to claim 7, characterized in that at least one part of quasi-logic circuits of the feedthrough cells and the cap cell are wired as predetermined to form desired logic circuits.
With such a configuration, even if a circuit modification involving newly adding an inverter, AND, NAND, NOR, or similar standard cell is required after the creation of a layout plan, a standard cell having such a logic circuit can be formed only by changing the wiring each quasi-logic circuit; hence, it is possible to reduce the cost and time for the fabrication of exposure masks.